1. Technical Field
This disclosure relates to a semiconductor device having a buried gate.
2. Related Art
In recent years, manufacturing methods of semiconductor devices such as dynamic random access memories (DRAMs) have been developed to improve the degree of integration. Thus, various methods have been investigated to ensure reliability of semiconductor devices while the degree of integration increases by applying a buried gate.
Buried gate structures may considerably reduce parasitic capacitance between a gate and a bit line by burying the gate in an active region. Therefore, sensing margins of memory devices are improved by applying a buried gate.
However, when a buried gate is applied, since a distance between a metal line and the buried gate is increased, misalignment is more likely to occur when a contact which connects a sub word line driver and the buried gate, is formed.
When misalignment of the contact occurs, the contact and a substrate are connected, which may cause current leakage in which current flows out to the substrate.